FPGA DSP Xilinx ISE Desgin Suite V11.1
ISE Design Suite for Xilinx world-class within the FPGA, DSP and embedded processing system design tools, evaluation has become very easy.
Currently, FPGA design has been fixed structure of the chip design has become equally complex, the door increase in the number and progress of the production process makes the FPGA come to the forefront of technology. FPGA prototyping is no longer merely as a platform for today's multi-million gate FPGA devices using advanced 45nm manufacturing process, price also has a considerable competitive edge, fully capable of supporting high-volume product design. Taking into account the high degree of flexibility and programmability of traditional advantages of convenience and design, FPGA, in many cases have already become the best option, can be widely used in computer, communications, consumer and automotive markets in a number of demanding and cost-sensitive??. Therefore, FPGA design tools environment must keep pace with the development of the corresponding device.
With the increasing complexity of FPGA designs, and the advanced production technology and constant introduction of new design implementation challenges, designers want to design tool solutions that better tools while improving performance, higher efficiency and richer functionality. One of the most concern is the design tool throughput capacity (ie, faster running time), ease of use and productivity. Is the only way to achieve faster timing closure and design iterations. Designers also need advanced capabilities to address the timing and low-power and other issues.
Meanwhile, the design is also different from integration, so the design team need to meet all the design options to achieve a comprehensive solution. Through an integrated environment for the completion of logic, embedded and DSP applications designed to increase productivity and, through the system on chip (SoC) FPGA promotion of a genuine system-level design.
Xilinx, an innovative way for its award-winning has been widely used in ISE ® launched a new version of the suite of tools to design solutions once again set a new standard, and its latest high-performance Virtex ® -5 and low-cost Spartan ® -3 FPGA provides a more powerful support. With the new ISE Design Suite 11.1, Xilinx properly address the problem of using high-level FPGA designer to design the most serious challenge faced by, and for the first time provide a unified logic, embedded and DSP application designers need to solution.
In the past few years, ISE has been an independent user surveys as the industry's best solution. Based on its consistent leadership, Xilinx now offers a new front-back covering the entire design process, full-featured enhanced design environment for complex FPGA designs can provide high-performance, high productivity and key features. ISE Design Suite 11.1 for the design process at every step to provide an intuitive productivity enhancement tools, covering from the system-level design exploration, software development and HDL-based hardware design, until the validation, debugging and PCB design integration of all the design process.
The pursuit of higher performance engineers are never satisfied, especially now that the design of the increasing scale and more complex. ISE Design Suite 11.1 Version greatly speed up the design to achieve speed, running speed an average of twice as fast. Therefore, the design can be completed in one day time, several design iterations. This enhanced design environment is also provided SmartXplorer technology. SmartXplorer technical expertise to resolve the designers faced timing closure and productivity of the development of these two formidable challenges. SmartXplorer technical support in a multi-platform distributed processing on a Linux host, you can more times a day to complete the implementation process. Through the use of distributed processing and multiple implementation strategies, performance can increase as much as 38%. SmartXplorer technology also provides a number of tools that allows users to report on the use of independent monitoring of the timing for each running instance.
PlanAhead Lite and policy-based approach provides the ultimate productivity of support for the implementation of
Design tools, and fast running speed is just not enough, designers also need more efficient methods and features to dramatically improve productivity.
ISE Design Suite 11.1 with award-winning Xilinx PlanAhead ™ design analysis tools provided by the power used in conjunction. PlanAhead ™ design analysis tool provides the layout of the planning and analysis capabilities can greatly reduce design time. PlanAhead can improve between synthesis and place and route process efficiency. The use of the critical path visualization and layout of the scale of view, designers can improve performance. This can greatly reduce design iterations and shorten the design iterations time. This approach allows designers to the design of large-scale divided into smaller, more manageable blocks and focus on optimizing each module, thereby enhancing the performance and quality throughout the design.
ISE ® Foundation ™ of the PlanAhead Lite tool provides the user with a full-featured PlanAhead design and analysis tool has a powerful floorplanning and analysis capabilities of a subset of. Provided free of charge, PlanAhead Lite features the revolutionary PinAhead technology. This intuitive solution designed to simplify the management of the interface between the target FPGA and PCB complexity. PinAhead technical support at an earlier stage in the design of intelligent pinout definition to avoid the usual occurred late in the design of the layout associated with the pin changes. Such a change in the past usually have to be completed through interactive pin layout design scale inspection. The PinAhead tool, pin assignment is completed, you can also use a comma-separated values (CSV) files or via VHDL or Verilog header file output I / O port information.
ISE Design Suite11.1 the introduction of further simplifies the process of determining optimal implementation settings. Now the designer can set up their own unique requirements and design goals, which can be the greatest performance, optimize device utilization, reduce dynamic power, or the shortest implementation time. For example, by specifying "area reduction" (reducing the area) as the main objective, the designer can get an average of 10% of the logic utilization.
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